general description the max9389 is a fully differential, high-speed, low-jitter,8-to-1 ecl/pecl multiplexer (mux) with dual output buffers. the device is designed for clock and data distri- bution applications, and features extremely low propa- gation delay (310ps typ) and output-to-output skew (30ps max). three single-ended select inputs, sel0, sel1, and sel2, control the mux function. the mux select inputs are com- patible with ecl/pecl logic, and are internally refer- enced to the on-chip reference output (v bb1 , v bb2 ), nominally v cc - 1.425v. the select inputs accept signals between v cc and v ee . internal pulldowns to v ee ensure a low default condition if the select inputs are left open.the differential inputs d_, d_ can be configured to accept a single-ended signal when the unused comple-mentary input is connected to the on-chip reference output (v bb1 , v bb2 ). all the differential inputs have internal bias and clamping circuits that ensure a lowoutput state when the inputs are left open. the max9389 operates with a wide supply range v cc - v ee of 2.375v to 5.5v. the device is offered in 32-pin tqfp and thin qfn packages, and operates over the -40? to +85? extended temperature range. applications high-speed telecom and datacom applicationscentral-office backplane clock distribution dslam/dlc features ? 310ps propagation delay ? guaranteed 2.7ghz operating frequency ? 0.3ps rms random jitter ? <30ps output-to-output skew ? -2.375v to -5.5v supplies for differentiallvecl/ecl ? +2.375v to +5.5v supplies for differentiallvpecl/pecl ? outputs low for open inputs ? dual output buffers ? >2kv esd protection (human body model) max9389 differential 8:1 ecl/pecl multiplexer with dual output buffers ________________________________________________________________ maxim integrated products 1 max9389 tqfp top view 32 28 293031 25 26 27 q0q0 v cc q1 v ee q1v cc sel2 10 13 15 14 16 11 12 9 d2d3 d2d4 d3d5 d4d5 17 18 19 20 21 22 23 sel0 24 sel1v cc d7 d7d6 d6 v ee 2 3 4 5 6 7 8 v cc d1 d1 d0 d0 v bb1 v bb2 1 v cc pin configurations ordering information v bb1 v bb2 v cc v ee v cc v ee mux 8:1 180k 180k 165k 180k 232k d0 d0d1 d1d2 d2d3 d3 d4 sel0sel1 sel2 d4 q0 q0q1 q1 d_ d_ max9389 v ee d5 d5d6 d6 d7 d7 functional diagram 19-2688; rev 0; 1/03 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range pin-package max9389ehj -40 c to +85 c 32 tqfp max9389etj* -40 c to +85 c 32 thin qfn pin configurations continued at end of data sheet. * future product contact factory for availability. downloaded from: http:///
max9389 differential 8:1 ecl/pecl multiplexer with dual output buffers 2 _______________________________________________________________________________________ absolute maximum ratings dc electrical characteristics(v cc - v ee = 2.375v to 5.5v, outputs loaded with 50 ? 1% to v cc - 2v. typical values are at v cc - v ee = 3.3v, v ihd = v cc - 1v, v ild = v cc - 1.5v, unless otherwise noted.) (notes 1 4) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v cc - v ee ..............................................................-0.3v to +6.0v inputs (d_, d_ , sel_) to v ee ......................-0.3v to (v cc + 0.3v) d_ to d_ ............................................................................... 3.0v continuous output current .................................................50ma surge output current........................................................100ma v bb _ sink/source current ..............................................?00? continuous power dissipation (t a = +70 c) 32-lead tqfp (derate 13.1mw/ c above +70 c) ...1047mw ja in still air..........................................................+76 c/w jc .........................................................................+25 c/w 32-lead qfn (derate 21.3mw/ c above +70 c) .....1702mw ja in still air..........................................................+47 c/w jc ...........................................................................+2 c/w operating temperature range ...........................-40 c to +85 c junction temperature ......................................................+150 c storage temperature range .............................-65 c to +150 c esd protectionhuman body model (d_, d_ , q_, q_ , sel_, v bb _) ............. 2kv soldering temperature (10s) ...........................................+300 c -40 c +25 c +85 c parameter symbol conditions min typ max min typ max min typ max units input (d_, d_ , sel_) single-endedinput high voltage v ih v bb_ connected to the unused input, figure 1 v cc - 1.225 v cc - 0.880 v cc - 1.225 v cc - 0.880 v cc - 1.225 v cc - 0.880 v single-endedinput low voltage v il v bb_ connected to the unused input, figure 1 v cc - 1.945 v cc - 1.625 v cc - 1.945 v cc - 1.625 v cc - 1.945 v cc - 1.625 v differential inputhigh voltage v ihd figure 1 v ee + 1.2 v cc v ee + 1.2 v cc v ee + 1.2 v cc v differential inputlow voltage v ild figure 1 v ee v cc - 0.095 v ee v cc - 0.095 v ee v cc - 0.095 v v cc - v ee < 3.0v 0.095 v cc - v ee 0.095 v cc - v ee 0.095 v cc - v ee differential inputvoltage v ihd - v ild figure 1 v cc - v ee 3.0v 0.095 3.000 0.095 3.000 0.095 3.000 v input current i in v ih, v il, v ihd, v ild -60 +60 -60 +60 -60 +60 ? output (q_, q_ ) single-endedoutput high voltage v oh figure 2 v cc - 1.145 v cc - 0.895 v cc - 1.145 v cc - 0.895 v cc - 1.145 v cc - 0.895 v downloaded from: http:///
max9389 differential 8:1 ecl/pecl multiplexer with dual output buffers _______________________________________________________________________________________ 3 dc electrical characteristics (continued)(v cc - v ee = 2.375v to 5.5v, outputs loaded with 50 ? 1% to v cc - 2v. typical values are at v cc - v ee = 3.3v, v ihd = v cc - 1v, v ild = v cc - 1.5v, unless otherwise noted.) (notes 1 4) -40 c +25 c +85 c parameter symbol conditions min typ max min typ max min typ max units single-endedoutput low voltage v ol figure 2 v cc - 1.945 v cc - 1.695 v cc - 1.945 v cc - 1.695 v cc - 1.945 v cc - 1.695 v differentialoutput voltage v oh - v ol figure 2 650 830 650 840 650 840 mv reference output (v bb _ ) referencevoltage output v bb1 v bb2 i bb1 + i bb2 = 0.5ma (note 5) v cc - 1.525 v cc - 1.425 v cc - 1.325 v cc - 1.525 v cc - 1.425 v cc - 1.325 v cc - 1.525 v cc - 1.425 v cc - 1.325 v power supply supply current i ee (note 6) 50 70 53 70 55 70 ma ac electrical characteristics(v cc - v ee = 2.375v to 5.5v, outputs loaded with 50 ? 1% to v cc - 2v, v ihd - v ild = 0.15v to 1v, f in 2.5ghz, input duty cycle = 50%, input transition time = 125ps (20% to 80%). typical values are at v cc - v ee = 3.3v, v ihd = v cc - 1v, v ild = v cc - 1.5v, f in = 622 mhz, input duty cycle = 50%, input transition time = 125ps (20% to 80%.)) (note 7) -40 c +25 c +85 c parameter symbol conditions min typ max min typ max min typ max units differential input-to-output delay t plhd , t phld figure 2 216 301 370 237 310 416 255 329 456 ps sel_-to-outputdelay t plh2 , t phl2 figure 4, inputtransition time = 500ps (20% to 80%) (note 8) 1.34 2 1.25 2 1.44 2 ns output-to-outputskew t skoo figure 5 (note 9) 15 15 30 ps input-to-outputskew t skio figure 6 (note 10) 50 50 55 ps part-to-partskew t skpp (note 11) 125 150 160 ps f in = 156mhz 0.3 1.15 0.3 1.15 0.3 1.15 f in = 622mhz 0.3 1.15 0.3 1.15 0.3 1.15 added randomjitter (note 12) t rj clockpattern f in = 2.5ghz 0.3 1.15 0.3 1.15 0.3 1.15 ps rms f in = 156mbps 33 95 33 95 33 95 addeddeterministic jitter (note 12) t dj prbs2 23 - 1 f in = 622mbps 21 61 21 61 21 61 ps p-p downloaded from: http:///
max9389 differential 8:1 ecl/pecl multiplexer with dual output buffers 4 _______________________________________________________________________________________ ac electrical characteristics (continued)(v cc - v ee = 2.375v to 5.5v, outputs loaded with 50 ? 1% to v cc - 2v, v ihd - v ild = 0.15v to 1v, f in 2.5ghz, input duty cycle = 50%, input transition time = 125ps (20% to 80%). typical values are at v cc - v ee = 3.3v, v ihd = v cc - 1v, v ild = v cc - 1.5v, f in = 622 mhz, input duty cycle = 50%, input transition time = 125ps (20% to 80%.)) (note 7) -40 c +25 c +85 c parameter symbol conditions min typ max min typ max min typ max units switchingfrequency f max v oh - v ol 300mv, figure 2 2.7 2.7 2.7 ghz select togglefrequency f sel v oh - v ol 300mv, figure 4 100 100 100 mhz output rise andfall time (20% to 80%) t r , t f figure 2 67 105 138 74 117 155 81 128 165 ps note 1: measurements are made with the device in thermal equilibrium. note 2: current into an i/o pin is defined as positive. current out of an i/o pin is defined as negative. note 3: dc parameters production tested at t a = +25 c and guaranteed by design over the full operating temperature range. note 4: single-ended data input operation using v bb _ is limited to (v cc - v ee ) 3.0v. note 5: use v bb_ only for inputs that are on the same device as the v bb_ reference. note 6: all pins open except v cc and v ee . note 7: guaranteed by design and characterization. limits are set at 6 sigma. note 8: measured from the 50% point of the input signal with the 50% point equal to v bb , to the 50% point of the output signal. note 9: measured between outputs of the same part at the signal crossing points for a same-edge transition. note 10: measured between input-to-output paths of the same part at the signal crossing points for a same-edge transition of thedifferential input signal. note 11: measured between outputs of different parts at the signal crossing points under identical conditions for a same-edgetransition. note 12: device jitter added to the differential input signal. supply current vs. temperature max9389 toc01 temperature ( c) supply current (ma) 60 35 -15 10 42.5 45.0 47.5 50.0 52.5 55.0 57.5 60.040.0 -40 85 all pins are open except v cc and v ee differential output voltage (v oh - v ol ) vs. frequency max9389 toc02 frequency (ghz) differential output voltage (mv) 2.5 2.0 1.5 1.0 0.5 300 400 500 600 700 800 900200 0 3.0 output rise/fall time vs. temperature max9389 toc03 rise/fall time (ps) 100 110 120 130 140 150 90 temperature ( c) 60 35 10 -15 -40 rise fall 85 typical operating characteristics (v cc - v ee = 3.3v, v ihd = v cc - 1v, v ild = v cc - 1.5v, outputs loaded with 50 ? 1% to v cc - 2v, f in = 622mhz, input duty cycle = 50%, input transition time = 125ps (20% to 80%), unless otherwise noted.) downloaded from: http:///
max9389 differential 8:1 ecl/pecl multiplexer with dual output buffers _______________________________________________________________________________________ 5 propagation delay vs. high voltage of differential input (v ihd ) max9389 toc04 v ihd (v) propagation delay (ps) 3.0 2.7 2.4 2.1 1.8 1.5 276 292 308 324 340260 1.2 3.3 v ihd - v ild = 150mv propagation delay vs. temperature max9389 toc05 temperature ( c) propagation delay (ps) 60 35 10 -15 270 290 310 330 350250 -40 t phl t plh 85 typical operating characteristics (continued) (v cc - v ee = 3.3v, v ihd = v cc - 1v, v ild = v cc - 1.5v, outputs loaded with 50 ? 1% to v cc - 2v, f in = 622mhz, input duty cycle = 50%, input transition time = 125ps (20% to 80%), unless otherwise noted.) pin description pin name function 1, 8, 22, 26, 29 v cc positive supply input. bypass each v cc to v ee with 0.1? and 0.01? ceramic capacitors. place the capacitors as close to the device as possible with the smaller value capacitor closest to the device. 2v bb2 reference output voltage 2. connect to the inverting or noninverting data input to provide a reference for single-ended operation. when used, bypass v bb2 to v cc with a 0.01? ceramic capacitor. otherwise leave open. 3v bb1 reference output voltage 1. connect to the inverting or noninverting data input to provide a reference for single-ended operation. when used, bypass v bb1 to v cc with a 0.01? ceramic capacitor. otherwise leave open. 4 d0 noninverting differential input 0. internal 232k to v cc and 180k to v ee . 5 d0 inverting differential input 0. internal 180k to v cc and 180k to v ee . 6 d1 noninverting differential input 1. internal 232k to v cc and 180k to v ee . 7 d1 inverting differential input 1. internal 180k to v cc and 180k to v ee . 9 d2 noninverting differential input 2. internal 232k to v cc and 180k to v ee . 10 d2 inverting differential input 2. internal 180k to v cc and 180k to v ee . 11 d3 noninverting differential input 3. internal 232k to v cc and 180k to v ee . 12 d3 inverting differential input 3. internal 180k to v cc and 180k to v ee . 13 d4 noninverting differential input 4. internal 232k to v cc and 180k to v ee . 14 d4 inverting differential input 4. internal 180k to v cc and 180k to v ee . 15 d5 noninverting differential input 5. internal 232k to v cc and 180k to v ee . 16 d5 inverting differential input 5. internal 180k to v cc and 180k to v ee . 17, 32 v ee negative supply input 18 d6 noninverting differential input 6. internal 232k to v cc and 180k to v ee . 19 d6 inverting differential input 6. internal 180k to v cc and 180k to v ee . downloaded from: http:///
max9389 differential 8:1 ecl/pecl multiplexer with dual output buffers 6 _______________________________________________________________________________________ pin description (continued) pin name function 20 d7 noninverting differential input 7. internal 232k to v cc and 180k to v ee . 21 d7 inverting differential input 7. internal 180k to v cc and 180k to v ee . 23 sel0 select logic input 0. internal 165k pulldown to v ee . 24 sel1 select logic input 1. internal 165k pulldown to v ee . 25 sel2 select logic input 2. internal 165k pulldown to v ee . 27 q1 inverting output 1. typically terminate with 50 resistor to v cc - 2v. 28 q1 noninverting output 1. typically terminate with 50 resistor to v cc - 2v. 30 q0 inverting output 0. typically terminate with 50 resistor to v cc - 2v. 31 q0 noninverting output 0. typically terminate with 50 resistor to v cc - 2v. ep exposed pad (qfn package only). connect to v ee . differential input voltage definition v cc v ee v cc v ih v il v bb v ee v ihd - v ild v ihd (max) v ild (max) v ihd (min) v ild (min) v ihd - v ild single-ended input voltage definition figure 1. input definitions v oh v ol v ihd - v ild v oh - v ol v oh - v ol v oh - v ol v ihd t plhd t r t f t phld v ild 20% 80% differential output waveform 0v (differential) 20% 80% d_q_ q_ - q_ q_ d_ figure 2. differential input-to-output propagation delay timingdiagram v oh - v ol t plh1 t phl1 v oh v ol v ih v bb v bb v il d_ when d_ = v bb q_q_ d_ when d_ = v bb or figure 3. single-ended input-to-output propagation delaytiming diagram v oh - v ol t plh2 t phl2 v oh v ol v ih v ihd v bb v il v ild v ihd - v ild q_ d_, d1 q_ d_, d1 sel_ = v il or open selo figure 4. select input (sel0) to output (q_, q_ ) delay timing diagram downloaded from: http:///
detailed description the max9389 is a fully differential, high-speed, low-jitter8-to-1 ecl/pecl mux with dual output buffers. the device is designed for clock and data distribution appli- cations, and features extremely low propagation delay (310ps typ) and output-to-output skew (30ps max). three single-ended select inputs, sel0, sel1, and sel2, control the mux function ( see table 1). the mux select inputs are compatible with ecl/pecl logic, andare internally referenced to the on-chip reference output (v bb1 , v bb2 ), nominally v cc - 1.425v. the select inputs accept signals between v cc and v ee . internal 165k pulldowns to v ee ensure a low default condition if the select inputs are left open. leaving sel0, sel1, andsel2 open selects the d0, d0 inputs by default. the differential inputs d_, d_ can be configured to accept a single-ended signal when the unused comple-mentary input is connected to the on-chip reference voltage (v bb1 , v bb2 ) . voltage reference outputs v bb1 and v bb2 provide the reference voltage needed for sin- gle-ended operations. a single-ended input of at leastv bb _ ?00mv or a differential input of at least 100mv switches the outputs to the v oh and v ol levels speci- fied in the dc electrical characteristics table . the maxi- mum magnitude of the differential input from d_ to d_ is 3.0v. this limit also applies to the difference between a single-ended input and any reference voltage input. * default output when sel0, sel1, and sel2 are left open. single-ended operation the recommended supply voltage for single-endedoperation is 3.0v to 3.8v. the differential inputs (d_, d_ ) can be configured to accept single-ended inputs when operating at supply voltages greater than 2.725v.in single-ended mode operation, the unused comple- mentary input needs to be connected to the on-chip reference voltage, v bb1 or v bb2 , as a reference. for example, the differential d_, d_ inputs are converted to a noninverting, single-ended input by connecting v bb1 or v bb2 to d_ and connecting the single-ended input to d_. similarly, an inverting input is obtained by connect-ing v bb1 or v bb2 to d_ and connecting the single- ended input to d_ . the single-ended input can be driven to v cc or v ee or with a single-ended lvpecl/lvecl signal. max9389 differential 8:1 ecl/pecl multiplexer with dual output buffers _______________________________________________________________________________________ 7 t skoo t skoo q0q0 q1 q1 figure 5. output-to-output skew (t skoo ) definition d1?7 d0 d0 d1?7 q0 q0q0 q0 t skio = | t plhd * - t plhd ** | or | t phld * - t phld ** | t plhd *t phld * t plhd ** t phld ** figure 6. input-to-output skew (t skio ) definition table 1. mux select input truth table data output sel0 sel1 sel2 d0* l or open l or open l or open d1 h l or open l or open d2 l or open h l or open d3 h h l or open d4 l or open l or open h d5 h l or open h d6 l or open h h d7 h h h downloaded from: http:///
max9389 in single-ended operation, ensure that the supply volt-age (v cc -v ee ) is greater than 2.725v. the input high minimum level must be at least (v ee + 1.2v) or higher for proper operation. the reference voltage v bb must be at least (v ee + 1.2v) because it becomes the high- level input when a single-ended input swings below it.the minimum v bb output for the max9389 is (v cc - 1.525v). substituting the minimum v bb output for (v bb = v ee + 1.2v) results in a minimum supply (v cc - v ee ) of 2.725v. rounding up to standard supplies gives therecommended single-ended operating supply ranges (v cc - v ee ) of 3.0v to 5.5v. when using the v bb reference output, bypass it with a 0.01? ceramic capacitor to v cc . if v bb is not being used, leave it unconnected. the v bb reference can source or sink a total of 0.5ma (shared between v bb1 and v bb2 ), which is sufficient to drive eight inputs. applications information output termination terminate each output with a 50 to v cc - 2v or use an equivalent thevenin termination. terminate each q_and q_ output with identical termination for minimal dis- tortion. when a single-ended signal is taken from thedifferential output, terminate both q_ and q_ . ensure that the output current does not exceed the cur-rent limits specified in the absolute maximum ratings table. under all operating conditions, the device s total thermal limits should not be exceeded. supply bypassing bypass each v cc to v ee with high-frequency surface- mount ceramic 0.1? and 0.01? capacitors. for pecl,bypass each v cc to v ee . for ecl, bypass each v ee to v cc . place the capacitors as close to the device as pos- sible with the 0.01? capacitor closest to the device pins.use multiple vias when connecting the bypass capacitors to ground. when using the v bb1 or v bb2 reference out- puts, bypass each one with a 0.01? ceramic capacitorto v cc . if the v bb1 or v bb2 reference outputs are not used, they can be left open. traces circuit board trace layout is very important to maintain thesignal integrity of high-speed differential signals. maintaining integrity is accomplished in part by reducing signal reflections and skew, and increasing common- mode noise immunity. signal reflections are caused by discontinuities in the 50 characteristic impedance of the traces. avoid discontinuities by maintaining the distance between differential traces, not using sharp corners or using vias. maintaining distance between the traces also increases common-mode noise immunity. reducing signal skew is accomplished by matching the electrical length of the differential traces. chip information transistor count: 716process: bipolar differential 8:1 ecl/pecl multiplexer with dual output buffers 8 _______________________________________________________________________________________ 3231 30 29 28 27 26 v ee q0q0 v cc q1q1 v cc 25 sel2 9 1011 12 13 14 15 d2d2 d3 d3d4 d4d5 16 d5 17 18 19 20 21 22 23 v ee note: v ee is connected to the undersidemetal slug. d6d6 d7d7 v cc sel0 8 7 6 5 4 3 2 v cc d1 d1 d0d0 v bb1 v bb2 max9389 thin qfn 1 v cc 24 sel1 top view pin configurations (continued) downloaded from: http:///
max9389 differential 8:1 ecl/pecl multiplexer with dual output buffers _______________________________________________________________________________________ 9 package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline information, go to www.maxim-ic.com/packages .) 32l tqfp, 5x5x01.0.eps downloaded from: http:///
max9389 differential 8:1 ecl/pecl multiplexer with dual output buffers maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 10 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2003 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline information, go to www.maxim-ic.com/packages .) qfn thin.eps d2 (nd-1) x e e d c pin # 1 i.d. (ne-1) x e e/2 e 0.08 c 0.10 c a a1 a3 detail a 0.15 c b 0.15 c a document control no. 21-0140 package outline 16, 20, 28, 32l, qfn thin, 5x5x0.8 mm proprietary information approval title: c rev. 2 1 e2/2 e2 0.10 m c a b pin # 1 i.d. b 0.35x45 l d/2 d2/2 l c l c e e l c c l k k l l 2 2 21-0140 rev. document control no. approval proprietary information title: common dimensions exposed pad variations 1. dimensioning & tolerancing conform to asme y14.5m-1994. 2. all dimensions are in millimeters. angles are in degrees. 3. n is the total number of terminals. 4. the terminal #1 identifier and terminal numbering convention shall conform to jesd 95-1 spp-012. details of terminal #1 identifier are optional, but must be located within the zone indicated. the terminal #1 identifier may be either a mold or marked feature. 5. dimension b applies to metallized terminal and is measured between 0.25 mm and 0.30 mm from terminal tip. 6. nd and ne refer to the number of terminals on each d and e side respectively. 7. depopulation is possible in a symmetrical fashion. 8. coplanarity applies to the exposed heat sink slug as well as the terminals.9. drawing conforms to jedec mo220. notes: 10. warpage shall not exceed 0.10 mm. c package outline 16, 20, 28, 32l, qfn thin, 5x5x0.8 mm downloaded from: http:///
|
